The present invention generally relates to semiconductor memory devices and more particularly to a dynamic random access memory.
A typical dynamic random access memory (DRAM) has a memory cell that includes a transfer transistor and a memory capacitor. Information is stored in the memory capacitor as electric charges. With the persistent demand of increased memory capacity and integration density, the area allowed for the transistor and the capacitor decreases ever and ever.
FIG. 1 shows an overall construction of a typical conventional DRAM.
Referring to FIG. 1, there is provided a substrate 1 on which a strip-like region 2 for word line decoder is formed in a first direction. Further, a plurality of strip-like regions 3 for sense amplifiers and column decoders are formed on the substrate at both sides of the region 2 in a second direction substantially perpendicular to the first direction. On the substrate 1, there are provided a number of cell blocks 4 along the region 3. There are formed a number of cell blocks 4 on the substrate 1 arranged in a row and column formation. From the word line decoder in the region 2, a number of word lines WL extend in the second direction parallel with each other. Similarly, a number of bit lines BL extend from each region 3 in the first direction parallel with each other.
FIG. 2 shows a part of the DRAM of FIG. 1 in an enlarged scale.
Referring to FIG. 2, the word line WL of FIG. 1 corresponds to a conductor 11 that extends vertical in FIG. 1, while the bit line BL corresponds to a conductor 12 extending laterally in the drawing. Further, there are provided a number of memory cells C each connected with a word line conductor 11 and a bit line conductor 12 at a contact hole 11a and a contact hole 12a.
FIG. 11 shows a cross-sectional view of the memory cell C taken along a line 1--1' of FIG. 2.
Referring to FIG. 3A, the memory cell C is formed in a region of the substrate 1 defined by a field oxide region 1a, wherein the substrate 1 is formed with a source region 1b and a drain region 1c with a gate electrode 11 provided on the substrate 1 in correspondence to a channel region located in the substrate 1 between the source region 1b and the drain region 1c. The source region 1b, the drain region 1c and the gate 11 form a transfer transistor T that forms the memory cell C. As usual, the gate electrode 11 is separated from the substrate 1 by a thin gate oxide film.
It should be noted that the gate electrode 11 coincides with the word line 11 of FIG. 2 and may be formed of polysilicon. On the other hand, the drain region 1c is contacted with a polysilicon electrode 14a that extends upwards on the substrate 1 and spreads laterally along an insulator layer 13 that is deposited on the substrate 1 to bury the gate electrode 11 and the field oxide region 1a. Thereby, the polysilicon electrode 14a forms an electrode of a memory cell capacitor CAP.
On the electrode 13, a thin film 15 of dielectric material such as silicon nitride is provided and another polysilicon layer 14b is provided to cover the silicon nitride film 15 at a side opposite to the side that is contacted with the polysilicon electrode 14a. Thereby, the electrode 14b forms an electrode of the memory capacitor CAP opposing the electrode 14a. It should be noted that this electrode 14b may extend throughout the memory cell block 4 shown in FIG. 1 as a conductive sheet except for a cutout formed in correspondence to the contact hole 12a where the bit line 12 makes a contact with the memory cell transistor T. Further, the capacitor CAP is buried under an insulator layer 16.
Referring to FIG. 3A again, the source region 1b of the transistor T is contacted with a polysilicon layer that acts as the bit line 12 at the contact hole 12a. This polysilicon layer 12 extends along the insulator layer 16 that covers the capacitor C in the direction of the bit line and forms a conductor strip of polysilicon extending in the lateral direction in the plan view of FIG. 2.
The bit line conductor 12 is buried under an insulator layer 17 on which a number of conductor strips l1b are provided parallel with each other in correspondence to the gate electrode or the word line 11. The conductor strip 11b may be made of aluminum and is contacted with the polysilicon word line 11 at the contact hole 11a.
FIG. 3B shows the connection of the polysilicon word line 11 and the aluminum strip 11b at the contact hole 11a, wherein FIG. 3B is a cross-sectional view taken along a line 2--2' of FIG. 2. It should be noted that the contact hole 11a is formed on the field oxide region 1a with an offset from the memory cell C along the conductor strip 11. By supplying the word line selection signal along the aluminum conductor strip 11b that has a characteristically low resistivity, the time constant of the signal path connected to the gate of the memory cell transfer transistor T is reduced and a quick addressing of the memory cell is achieved. It should be noted that the word lines tend to extend for a distance much longer than the bit lines as can be seen in FIG. 1.
FIG. 4 shows another example of the conventional DRAM device, wherein FIG. 4 shows a cross-sectional view corresponding to the cross-sectional view of FIG. 3A. In this example, there is provided a polysilicon electrode 12b directly in contact with the source region 1b of the transistor T and the electrode 12b is contacted with the bit line 12 of aluminum at the contact hole 12a. The aluminum bit line is provided on the insulator layer 16, similarly to the case of the device of FIG. 3A.
In this example, too, the polysilicon word line 11 is connected to the aluminum word line 11b at the contact hole 11a offset from the memory cell C and thereby a quick response of the memory cell is achieved. In the present case, the response is improved further as a result of use of the aluminum conductor for the bit line in stead of using polysilicon bit lines. As the bit lines is connected to write amplifiers and the sense amplifiers, the decrease of resistivity in the bit lines by the use of aluminum for the bit lines contributes significantly on the improvement in the response of the memory device.
In the DRAM devices of the latter type in particular, there arises a problem in that, when the contact hole 12a is provided with a slight offset to the capacitor Cap due to the error in patterning and the like, the polysilicon electrode 12b may be contacted with the polysilicon electrode 14b. This risk obviously increases with decreasing size of the DRAM device. Further, the decreasing in the size of the DRAM invites inevitable decrease in the diameter of the contact hole 12a. When the diameter of the contact hole becomes excessively small, the deposition of aluminum in contact with the polysilicon electrode 12b at the contact hole 12a becomes difficult because of the poor step coverage of aluminum deposited by sputtering.
The problem of poor contact between the polysilicon electrode 12b and the aluminum bit line 12 is deteriorated further when the structure is applied to the DRAM device having a so-called stacked capacitor wherein the memory capacitor Cap is formed into a number of layers of dielectric films. When such a structure is adopted, the depth of the contact hole 12a becomes inevitably large and thereby the step coverage is degraded further. This means that the yield and reliability of the DRAM is decreased with increasing degree of miniaturizations.